• PCI-X
• Mini PCI
• PCI Local Bus
• PCI to PCI
• PCI 32bit
• PCI 64 bit
• PCI Mobile
• Small PCI
• PCI CD-ROM
• PCI 33mhz
• PCI 66mhz

What about duplex? (example - if the PCI bus can support 160mbps is that 80 mbps in and 80 mbps out? )

If you have is the speed limited by the PCI bus. (Example if I have 3 PCI network cards they can only support 160 mbps together because of the bus limitation) I am sure by the above - you can tell that I have know idea what I am talking about when it comes to PCI.

Also anyone know any of the above answers for ISA, EISA and AGP. Not that they use / have ISA and AGP network card today but who knows. :  Any help would be greatly appreciated. I would be more than happy to share my presentation with anyone who wants it after I get all the required info (ISA, EISA PCI, AGP, Anything else I missed ? )

Jay Cann - IT R&D Network Engineering - Genuity

Hi Jay,

Well, a lot of questions. I will try to give you an answer for the standard pci system. This system can be build either with 32bit or 64bit and could be run at 33MHz or 66MHz. There are some limitations concerning the bus load of such systems. 66MHz systems can be used inside a system wich is running without connectors. At least for the standard PC connectors I haven't heard about any 66MHz system. The organisation of the bus is similar to the ISA bus. A short connector in the PC means 32bit, a long (extended) connector means 64bit.

If you would calculate the performance of the system you ran in some trouble, because this depends on a lot of things: First, the bus system itself. For the calculation you need the number of bus cycles for a transfer. For a single transfer you need a minimum of 4 cycles. This means, if you transfers single bytes you would reach 33M / 4 cycles * 1 Byte = 8,25 MByte/s (66Mbit/s) But this is an absolute worst case and only for very, very badly desinged components.

The standard single beat transfer (one longword) results to 33M / 4 cycles * 4 Byte = 33 MByte/s (264Mbit/s)

If you would have high performance the components should strongly use burst accesses over the bus. For this you need a DMA controller inside the network chip, which can read data out of the mainboard. In this case the absolut needed cycles reduce (cycles = one for arbitration, one for adressing, n cycles for data, one cycle for termination). So, if you would transfer your data in burst of 8 longwords (you need a fifo with a minimum of 32 byte depth in the network chip) you need 11 cycles for the transfer. This results to 33M / 11 cycles * 32 Byte = 96 MByte/s (768Mbit/s)

Ok, for infinit bursts you would reach the theoretical limit of 132MByte/s, but never really think about it. The 96 MByte/s is a could value for the PC market. In our tests we really reach transfer rates of 80...100MByte/s (but for writing into the main memory).

For 64bit systems you can double the transfer rate and for 66MHz systems you double it again.

That's the truth for the bus system itself. The next point ist the real length of the the transfers. During the transfer the initiator and the target can force wait cycles and terminations with retry's. That depends, how fast the initiator (in this case your network card) can handle the data. Because you use gigabit cards, I think it will be very fast. But on the other side you have the PC PCI-Bridge to the main memory. During an access either the SDRAM could be in use by the processor or if it is free, it needs some time for the data access. This time results either in a termination with retry or wait states. In both cases you loose time. How much this slows down the transfer depends on the design of the PCI-Bridge and the main memory.

The transfer rate does primary not depend on the direction. But the problem in the PC is the following:

A DMA controller normally is created on the side of the data source. In this case the transfer would be initiated, if enough data is available. The data could be stored in a fifo inside the target and stored to memory a few cycles later (if the memory is ready). This results in a maximun bandwidth. In the case of the network cards the DMA controller for sending should be placed inside the PC based PCI bridge. But it is not available at this point. The result is, that reads out of the main memory of the PC are significant slower than writes to the memory. In this case I assume the result would be better for data writing to memory rather than reading.

Question to the other guys: Is this currently true ? Or is a DMA controller available in the north bridges ?

Unfortunatly I can give no black&white answer. If the system is designed well, you could get transfer rates up to 100MByte/s for a 32bit/33MHz system (400MByte for a 64bit/66MHz system). But the real transfer rate depends on all (!) components in the system. Look for the bottlenecks.

Greeting, Andreas Heiner